1. Field of the Invention
The present invention relates in general to a semiconductor process, and more particularly, to a method for forming narrow trench structures.
2. Description of the Related Art
In order to increase the integration of integrated circuits (ICs), one trend in the semiconductor industry is to make the semiconductor devices or device-to-device spacing as small as possible, thereby enabling fabrication of more semiconductor devices in the predetermined area on a chip to raise the operating speed and performance of ICs.
Metal oxide semiconductor (MOS) transistors are common semiconductor devices. The fabrication of the MOS transistor includes successively forming a gate dielectric layer, a conductive layer, and a photoresist layer on a substrate. Thereafter, lithography is performed on the photoresist layer to form gate patterns therein. Finally, the gate patterns are transferred onto the conductive layer by etching. Accordingly, line/space width is limited by the resolution of the available lithography equipment. As a result, the lithography resolution is critical for increasing device density. In other words, the IC integration is limited by photoresist properties and the light wavelength for exposure. The lithography resolution can be raised by specific photoresist or lithography equipment, but the fabrication cost may increase. In light of the foregoing, there exists a need for a method to increase the integration of ICs without being limited by lithography.
U.S. Pat. No. 5,254,218 discloses a method for forming narrow isolated trenches, wherein a conformable polysilicon layer is formed on the surface of the masking islands formed on a substrate and covers the substrate. Thereafter, a silicon oxide masking layer is formed on both sides of each masking island and covers the polysilicon layer on the substrate. Finally, the polysilicon layer on the upper surface and sidewall of each masking island is removed to form openings for defining narrow trenches. In this method, no specific photoresist or lithography equipment is required. The uniformity of the polysilicon layer formed by CVD with poor step coverage, is however reduced, due to the varying dimensions of the narrow trenches. Moreover, since the polysilicon layer on the substrate is covered by the silicon oxide masking layer, undercut occurs during etching of the uncovered polysilicon layer. As a result, the dimensions of the narrow trenches are difficult to precisely control.
Additionally, U.S. Pat. No. 6,355,528 discloses a method to form narrow structures using a dual damascene process, which employs an anisotropic etching to form spacers on the sidewalls of the masking islands. The space between each masking island is subsequently filled with another masking layer. Finally, the spacers are removed to form narrow openings for forming the narrow structures. The spacers formed by anisotropic etching, however, cannot have a vertical profile. As a result, the dimensions of the narrow structures are also difficult to precisely control.